1. Field of the Invention
The invention relates in general to a thin film transistor (TFT) structure and method of fabricating the same, and more particularly to the thin film transistor structure capable of reducing current leakage and method of fabricating the same.
2. Description of the Related Art
In the recent years, the development of semiconductor technology has really flourished. The size of the semiconductor device is greatly minimized, and the integration of the integrated circuit is thus increasing. When a semiconductor device is operated, instabilities of electrical characteristics are especially noticeable and easy to occur in the device with high integration. Therefore, stability is an important concern while fabricating a device with micro-size. For example, no excessive leakage current is observed when a TFT device is off (i.e. zero applied gate voltage).
FIG. 1 is a cross-sectional view of a conventional thin film transistor (TFT) device. A gate electrode 104 is formed by the usual photolithography and etch of a first metal layer formed on the substrate 120. The first metal layer is generally made of pure aluminum (Al), molybdenum (Mo), an alloy of aluminum and neodymium (AlNd), or a multi-layer made of the materials thereof.
Then, a gate insulation layer 106 is formed on the gate electrode 104. Above the gate insulation layer 106, an amorphous silicon layer (a-Si layer) 108 and an ohmic contact layer such as the n+ a-Si layer 110 are formed in order by the processes of deposition, photolithography and etch.
A second metal layer, made of titanium (Ti), molybdenum (Mo) or chromium (Cr), is then formed above the substrate 102. A source region 112 and a drain region 113 are formed by the usual photolithography and etch of a second metal layer. Also, a channel 114 is formed by opening the portion of the second metal layer relatively to the position of the gate electrode 104, for exposing the amorphous silicon layer 108. The channel 114 separates the source region 112 and the drain region 113.
Next, a passivation layer 116, such as a silicon nitride (SiNx) layer, is deposited over the substrate 102, and covers the source region 112 and the drain region 113. The channel 114 is also filled with the passivation layer 116. Also, a via (not shown in FIG. 1) is formed in the passivation layer 116 to expose the drain region 112, by photolithography and etch steps. Then, a transparent electrode layer (not shown in FIG. 1) is formed on the passivation layer 116, and fills the via. Finally, the transparent electrode layer is patterned by photolithography and etching.
Typically, the amorphous silicon layer 108 contains no dopant or impurity, so as called “intrinsic a-Si layer”. The contact between the n+ a-Si layer 110 and the intrinsic a-Si layer 108 is so called N-I junction. In the conventional structure of semiconductor device, electrons tend to flow to the passivation layer 116 in the channel 114 through the N-I junction, so that excessive current leakage appears frequently. This undesirable instability of the semiconductor device is an issue to be solved.